358 lines
8.5 KiB
C
358 lines
8.5 KiB
C
/*
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* lscpu-arm.c - ARM CPU identification tables
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*
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* Copyright (C) 2018 Riku Voipio <riku.voipio@iki.fi>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it would be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* The information here is gathered from
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* - ARM manuals
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* - Linux kernel: arch/armX/include/asm/cputype.h
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* - GCC sources: config/arch/arch-cores.def
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* - Ancient wisdom
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* - SMBIOS tables (if applicable)
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*/
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#include "lscpu.h"
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struct id_part {
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const int id;
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const char* name;
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};
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static const struct id_part arm_part[] = {
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{ 0x810, "ARM810" },
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{ 0x920, "ARM920" },
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{ 0x922, "ARM922" },
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{ 0x926, "ARM926" },
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{ 0x940, "ARM940" },
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{ 0x946, "ARM946" },
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{ 0x966, "ARM966" },
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{ 0xa20, "ARM1020" },
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{ 0xa22, "ARM1022" },
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{ 0xa26, "ARM1026" },
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{ 0xb02, "ARM11 MPCore" },
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{ 0xb36, "ARM1136" },
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{ 0xb56, "ARM1156" },
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{ 0xb76, "ARM1176" },
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{ 0xc05, "Cortex-A5" },
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{ 0xc07, "Cortex-A7" },
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{ 0xc08, "Cortex-A8" },
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{ 0xc09, "Cortex-A9" },
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{ 0xc0d, "Cortex-A17" }, /* Originally A12 */
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{ 0xc0f, "Cortex-A15" },
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{ 0xc0e, "Cortex-A17" },
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{ 0xc14, "Cortex-R4" },
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{ 0xc15, "Cortex-R5" },
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{ 0xc17, "Cortex-R7" },
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{ 0xc18, "Cortex-R8" },
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{ 0xc20, "Cortex-M0" },
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{ 0xc21, "Cortex-M1" },
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{ 0xc23, "Cortex-M3" },
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{ 0xc24, "Cortex-M4" },
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{ 0xc27, "Cortex-M7" },
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{ 0xc60, "Cortex-M0+" },
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{ 0xd01, "Cortex-A32" },
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{ 0xd03, "Cortex-A53" },
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{ 0xd04, "Cortex-A35" },
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{ 0xd05, "Cortex-A55" },
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{ 0xd06, "Cortex-A65" },
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{ 0xd07, "Cortex-A57" },
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{ 0xd08, "Cortex-A72" },
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{ 0xd09, "Cortex-A73" },
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{ 0xd0a, "Cortex-A75" },
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{ 0xd0b, "Cortex-A76" },
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{ 0xd0c, "Neoverse-N1" },
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{ 0xd0d, "Cortex-A77" },
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{ 0xd0e, "Cortex-A76AE" },
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{ 0xd13, "Cortex-R52" },
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{ 0xd20, "Cortex-M23" },
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{ 0xd21, "Cortex-M33" },
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{ 0xd41, "Cortex-A78" },
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{ 0xd42, "Cortex-A78AE" },
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{ 0xd4a, "Neoverse-E1" },
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{ 0xd4b, "Cortex-A78C" },
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{ -1, "unknown" },
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};
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static const struct id_part brcm_part[] = {
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{ 0x0f, "Brahma B15" },
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{ 0x100, "Brahma B53" },
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{ 0x516, "ThunderX2" },
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{ -1, "unknown" },
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};
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static const struct id_part dec_part[] = {
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{ 0xa10, "SA110" },
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{ 0xa11, "SA1100" },
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{ -1, "unknown" },
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};
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static const struct id_part cavium_part[] = {
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{ 0x0a0, "ThunderX" },
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{ 0x0a1, "ThunderX 88XX" },
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{ 0x0a2, "ThunderX 81XX" },
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{ 0x0a3, "ThunderX 83XX" },
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{ 0x0af, "ThunderX2 99xx" },
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{ -1, "unknown" },
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};
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static const struct id_part apm_part[] = {
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{ 0x000, "X-Gene" },
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{ -1, "unknown" },
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};
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static const struct id_part qcom_part[] = {
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{ 0x00f, "Scorpion" },
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{ 0x02d, "Scorpion" },
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{ 0x04d, "Krait" },
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{ 0x06f, "Krait" },
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{ 0x201, "Kryo" },
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{ 0x205, "Kryo" },
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{ 0x211, "Kryo" },
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{ 0x800, "Falkor V1/Kryo" },
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{ 0x801, "Kryo V2" },
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{ 0xc00, "Falkor" },
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{ 0xc01, "Saphira" },
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{ -1, "unknown" },
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};
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static const struct id_part samsung_part[] = {
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{ 0x001, "exynos-m1" },
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{ -1, "unknown" },
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};
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static const struct id_part nvidia_part[] = {
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{ 0x000, "Denver" },
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{ 0x003, "Denver 2" },
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{ 0x004, "Carmel" },
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{ -1, "unknown" },
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};
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static const struct id_part marvell_part[] = {
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{ 0x131, "Feroceon 88FR131" },
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{ 0x581, "PJ4/PJ4b" },
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{ 0x584, "PJ4B-MP" },
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{ -1, "unknown" },
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};
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static const struct id_part faraday_part[] = {
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{ 0x526, "FA526" },
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{ 0x626, "FA626" },
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{ -1, "unknown" },
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};
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static const struct id_part intel_part[] = {
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{ 0x200, "i80200" },
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{ 0x210, "PXA250A" },
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{ 0x212, "PXA210A" },
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{ 0x242, "i80321-400" },
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{ 0x243, "i80321-600" },
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{ 0x290, "PXA250B/PXA26x" },
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{ 0x292, "PXA210B" },
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{ 0x2c2, "i80321-400-B0" },
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{ 0x2c3, "i80321-600-B0" },
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{ 0x2d0, "PXA250C/PXA255/PXA26x" },
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{ 0x2d2, "PXA210C" },
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{ 0x411, "PXA27x" },
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{ 0x41c, "IPX425-533" },
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{ 0x41d, "IPX425-400" },
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{ 0x41f, "IPX425-266" },
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{ 0x682, "PXA32x" },
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{ 0x683, "PXA930/PXA935" },
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{ 0x688, "PXA30x" },
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{ 0x689, "PXA31x" },
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{ 0xb11, "SA1110" },
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{ 0xc12, "IPX1200" },
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{ -1, "unknown" },
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};
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static const struct id_part fujitsu_part[] = {
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{ 0x001, "A64FX" },
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{ -1, "unknown" },
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};
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static const struct id_part hisi_part[] = {
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{ 0xd01, "Kunpeng-920" }, /* aka tsv110 */
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{ -1, "unknown" },
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};
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static const struct id_part ft_part[] = {
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{ 0x662, "FT2000PLUS" },
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{ 0x663, "S2500" },
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{ -1, "unknown" },
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};
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static const struct id_part unknown_part[] = {
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{ -1, "unknown" },
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};
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struct hw_impl {
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const int id;
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const struct id_part *parts;
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const char *name;
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};
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static const struct hw_impl hw_implementer[] = {
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{ 0x41, arm_part, "ARM" },
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{ 0x42, brcm_part, "Broadcom" },
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{ 0x43, cavium_part, "Cavium" },
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{ 0x44, dec_part, "DEC" },
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{ 0x46, fujitsu_part, "FUJITSU" },
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{ 0x48, hisi_part, "HiSilicon" },
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{ 0x49, unknown_part, "Infineon" },
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{ 0x4d, unknown_part, "Motorola/Freescale" },
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{ 0x4e, nvidia_part, "NVIDIA" },
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{ 0x50, apm_part, "APM" },
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{ 0x51, qcom_part, "Qualcomm" },
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{ 0x53, samsung_part, "Samsung" },
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{ 0x56, marvell_part, "Marvell" },
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{ 0x61, unknown_part, "Apple" },
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{ 0x66, faraday_part, "Faraday" },
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{ 0x69, intel_part, "Intel" },
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{ 0x70, ft_part, "Phytium" },
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{ 0xc0, unknown_part, "Ampere" },
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{ -1, unknown_part, "unknown" },
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};
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static int parse_id(const char *str)
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{
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int id;
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char *end = NULL;
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if (!str || strncmp(str, "0x",2) != 0)
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return -EINVAL;
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errno = 0;
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id = (int) strtol(str, &end, 0);
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if (errno || str == end)
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return -EINVAL;
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return id;
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}
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#define parse_model_id(_cxt) (parse_id((_cxt)->model))
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static inline int parse_implementer_id(struct lscpu_cputype *ct)
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{
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if (ct->vendor_id)
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return ct->vendor_id;
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ct->vendor_id = parse_id(ct->vendor);
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return ct->vendor_id;
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}
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/*
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* Use model and vendor IDs to decode to human readable names.
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*/
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static int arm_ids_decode(struct lscpu_cputype *ct)
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{
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int impl, part, j;
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const struct id_part *parts = NULL;
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impl = parse_implementer_id(ct);
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if (impl <= 0)
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return -EINVAL; /* no ARM or missing ID */
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/* decode vendor */
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for (j = 0; hw_implementer[j].id != -1; j++) {
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if (hw_implementer[j].id == impl) {
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parts = hw_implementer[j].parts;
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free(ct->vendor);
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ct->vendor = xstrdup(hw_implementer[j].name);
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break;
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}
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}
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/* decode model */
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if (!parts)
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goto done;
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part = parse_model_id(ct);
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if (part <= 0)
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goto done;
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for (j = 0; parts[j].id != -1; j++) {
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if (parts[j].id == part) {
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free(ct->modelname);
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ct->modelname = xstrdup(parts[j].name);
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break;
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}
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}
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done:
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return 0;
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}
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/* use "rXpY" string as stepping */
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static int arm_rXpY_decode(struct lscpu_cputype *ct)
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{
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int impl, revision, variant;
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char *end = NULL;
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char buf[8];
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impl = parse_implementer_id(ct);
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if (impl != 0x41 || !ct->revision || !ct->stepping)
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return -EINVAL;
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errno = 0;
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revision = (int) strtol(ct->revision, &end, 10);
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if (errno || ct->revision == end)
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return -EINVAL;
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errno = 0;
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variant = (int) strtol(ct->stepping, &end, 0);
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if (errno || ct->stepping == end)
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return -EINVAL;
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snprintf(buf, sizeof(buf), "r%dp%d", variant, revision);
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free(ct->stepping);
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ct->stepping = xstrdup(buf);
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return 0;
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}
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static void arm_decode(struct lscpu_cxt *cxt, struct lscpu_cputype *ct)
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{
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if (!cxt->noalive && access(_PATH_SYS_DMI, R_OK) == 0)
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dmi_decode_cputype(ct);
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arm_ids_decode(ct);
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arm_rXpY_decode(ct);
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if (!cxt->noalive && cxt->is_cluster)
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ct->nr_socket_on_cluster = get_number_of_physical_sockets_from_dmi();
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}
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static int is_cluster_arm(struct lscpu_cxt *cxt)
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{
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struct stat st;
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if (!cxt->noalive
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&& strcmp(cxt->arch->name, "aarch64") == 0
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&& stat(_PATH_ACPI_PPTT, &st) < 0 && cxt->ncputypes == 1)
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return 1;
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else
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return 0;
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}
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void lscpu_decode_arm(struct lscpu_cxt *cxt)
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{
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size_t i;
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cxt->is_cluster = is_cluster_arm(cxt);
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for (i = 0; i < cxt->ncputypes; i++)
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arm_decode(cxt, cxt->cputypes[i]);
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}
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