The file "/sys/firmware/dmi/tables/DMI" always exists.
The dmi_decode_cputype() can provide more information then arm_smbios_decode().
So remove it to tidy the code.
Before this patch, we can get the output from Centos 7.9 who has
"/sys/firmware/dmi/entries/4-0/raw" and "/sys/firmware/dmi/tables/DMI":
----------------------------------------------------
BIOS Vendor ID: Ampere(TM)
Model name： Neoverse-N1
BIOS Model name: Ampere(TM) Altra(TM) Processor
----------------------------------------------------
After this patch which uses "/sys/firmware/dmi/tables/DMI", in Centos 7.9, we get:
----------------------------------------------------
BIOS Vendor ID: Ampere(TM)
Model name： Neoverse-N1
BIOS Model name: Ampere(TM) Altra(TM) Processor Q00-00 CPU @ 2.8GHz
BIOS CPU family: 257
----------------------------------------------------
Signed-off-by: Huang Shijie <shijie@os.amperecomputing.com>
The patch :367c85c47286 ("lscpu: use SMBIOS tables on ARM for lscpu")
relies on the existence of "/sys/firmware/dmi/entries/4-0/raw",
which may not exist in standard linux kernel.
But "/sys/firmware/dmi/tables/DMI" should exist and can provide the required
processor information.
This patch uses "/sys/firmware/dmi/tables/DMI"
to get the processor information:
Before this patch, in Ampere Altra platform, the lscpu output is:
---------------------------------------------
Architecture: aarch64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 160
On-line CPU(s) list: 0-159
Vendor ID: ARM
Model name: Neoverse-N1
Model: 1
Thread(s) per core: 1
Core(s) per socket: 80
Socket(s): 2
........................................
---------------------------------------------
After this patch, we can use get the lscpu output
in Ampere Altra platform:
---------------------------------------------
Architecture: aarch64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 160
On-line CPU(s) list: 0-159
Vendor ID: ARM
BIOS Vendor ID: Ampere(R)
Model name: Neoverse-N1
BIOS Model name: Ampere(R) Altra(R) Processor Q00-00 CPU @ 3.0GHz
Model: 1
Thread(s) per core: 1
Core(s) per socket: 80
Socket(s): 2
........................................
---------------------------------------------
[kzak@redhat.com: - s/sprintf/snprintf/]
Signed-off-by: Huang Shijie <shijie@os.amperecomputing.com>
Signed-off-by: Karel Zak <kzak@redhat.com>
Show the number of the number of physical socket even if the sysfs doesn't
have the physical socket information.
Note, lscpu shows the number of physical socket as 'Socket(s):' only if
root user runs it because accessing the DMI table requires root
privilege.
Signed-off-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
lscpu may show the wrong number of sockets if the machine is aarch64 and
doesn't have ACPI PPTT.
That's because lscpu shows the number of sockets by using a sysfs entry
(cpu/cpuX/topology/core_siblings). The sysfs entry is set by MPIDR_EL1
register if the machine doesn't have ACPI PPTT. MPIDR_EL1 doesn't show
the physical socket information directly. It shows the affinity level.
According to linux/arch/arm64/kernel/topology.c:store_cpu_topology(),
the top level of affinity is called as 'Cluster'.
Use Cluster instead of Socket on the machine which doesn't have ACPI PPTT.
This patch is useful for aarch64 machine which is based on ARM
SBBR v1.0 and v1.1, the specs don't require ACPI PPTT. ARM SBBR v1.2
requires ACPI PPTT.
Signed-off-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
After commit: 367c85c47 ("lscpu: use SMBIOS tables on ARM for lscpu"),
Model name for A64FX shows like as:
Model name: 461F0010
That's because 367c85c47 changes to get the modelname from Processor
Version of SMBIOS.
To fix that, use the hard corded table to show the "Model name" and
add two new lines; "BIOS Vendor ID" and "BIOS Model name" to show the
SMBIOS information.
lscpu shows the SMBIOS information when root user runs it because
accessing the SMBIOS information requires root privilege.
[kzak@redhat.com: - port the patch to new lscpu code]
Signed-off-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Signed-off-by: Karel Zak <kzak@redhat.com>
Over the past two years Arm has published further MIDR/part numbers
on https://developer.arm.com/ip-products/processors/cortex-a.
Lets sync the arm_part structure for A65, A76AE, A77 and A78*.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
ARM SBBR (Sever Base Boot Requirements) require SMBIOS tables, and
SMBIOS Type 4 describes the CPU manufacturer and model name (among other
details). If SMBIOS Type 4 is present, use it to extract these strings.
Example output (before and after the patch) on an HP m400, Lenovo HR330A,
and HPE Apollo 70:
[root@hp-m400 ~]# /usr/bin/lscpu | grep -i -e vendor -e model -e stepping
Vendor ID: APM
Model: 1
Model name: X-Gene
Stepping: 0x0
[root@hp-m400 ~]# ./lscpu | grep -i -e vendor -e model -e stepping
Vendor ID: AppliedMicro
Model: 1
Model name: X-Gene
Stepping: 0x0
[root@lenovo-hr330a ~]# /usr/bin/lscpu | grep -i -e vendor -e model -e stepping
Vendor ID: APM
Model: 2
Model name: X-Gene
Stepping: 0x3
[root@lenovo-hr330a ~]# ./lscpu | grep -i -e vendor -e model -e stepping
Vendor ID: Ampere(TM)
Model: 2
Model name: eMAG
Stepping: 0x3
[root@hpe-apollo-70 ~]# /usr/bin/lscpu | grep -i -e vendor -e model -e stepping
Vendor ID: Cavium
Model: 1
Model name: ThunderX2 99xx
Stepping: 0x1
[root@hpe-apollo-70 ~]# ./lscpu | grep -i -e vendor -e model -e stepping
Vendor ID: Cavium Inc.
Model: 1
Model name: Cavium ThunderX2(R) CPU CN9980 v2.1 @ 2.20GHz
Stepping: 0x1
[kzak@redhat.com: - move dmi_header to lscpu.h
- make arm_cpu_smbios() more robust for failed
open() and read()
- use original arm_cpu_decode() also on failed
arm_cpu_smbios()]
Signed-off-by: Jeffrey Bastian <jbastian@redhat.com>
Signed-off-by: Karel Zak <kzak@redhat.com>
Add an entry for the HiSilicon aarch64 part tsv110.
Another known alias for this part is TaishanV110, and it can be
found in the Kunpeng920/Hi1620 SoC.
Signed-off-by: John Garry <john.garry@huawei.com>
ARM has released docs for Cortex-A76, Neoverse-N1 and Neoverse-E1.
That means we know the midr partnums, so we can add them to the
human readable model name table.
Signed-off-by: Jeremy Linton <lintonrjeremy@gmail.com>
Add a handful of more rare cores. Broadcom Brahma cores are
used in Access Points and Faraday was used on some Network
Storage Devices.
Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
Karel Zak
Huang Shijie
Ville Skyttä
Masayoshi Mizuma
Jeremy Linton
Jeffrey Bastian
Shunsuke Nakamura
Tomoaki Teshima
Rosen Penev
John Garry
Jeremy Linton
Mark Sheppard
Riku Voipio