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lscpu: regression tests 

This patch added regression tests for lscpu. It tests lscpu for 3
architecutres, i386, x86_64 and ia64, with data from 3 different
machines each.

Signed-off-by: Cai Qian <qcai@redhat.com>
Signed-off-by: Karel Zak <kzak@redhat.com>
This commit is contained in:
Cai Qian 2008-08-14 13:15:43 +02:00 committed by Karel Zak
parent 928e9f327f
commit c2abd9a0a5
1217 changed files with 2805 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
tests/commands.sh.in
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@ -39,6 +39,7 @@ TS_CMD_CHECKTTY=${TS_CMD_CHECKTTY-"$TOPDIR/login-utils/checktty_test"}
TS_CMD_ISLOCAL=${TS_CMD_ISLOCAL-"$TOPDIR/login-utils/islocal_test"}
TS_CMD_HWCLOCK=${TS_CMD_HWCLOCK-"$TOPDIR/hwclock/hwclock"}
TS_CMD_LSCPU=${TS_CMD_LSCPU-"$TOPDIR/sys-utils/lscpu"}

27
tests/expected/ts-lscpu-i386-amdshanghai Normal file
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@ -0,0 +1,27 @@
CPU(s): 8
Thread(s) per core: 1
Core(s) per socket: 4
CPU socket(s): 2
Vendor ID: AuthenticAMD
CPU family: 16
Model: 4
Stepping: 0
CPU MHz: 1995.158
Virtualization: AMD-V
L1d cache: 512K
L1i cache: 512K
L2 cache: 512K
L3 cache: 6144K
# The following is the parsable format, which can be fed to other
# programs. Each different item in every column has an unique ID
# starting from zero.
# CPU,Core,Socket,Node,,L1d,L1i,L2,L3
0,0,0,,,0,0,0,0
1,1,0,,,1,1,1,1
2,2,0,,,2,2,2,2
3,3,0,,,3,3,3,3
4,4,1,,,4,4,4,4
5,5,1,,,5,5,5,5
6,6,1,,,6,6,6,6
7,7,1,,,7,7,7,7

16
tests/expected/ts-lscpu-i386-dellpe700 Normal file
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@ -0,0 +1,16 @@
CPU(s): 2
Thread(s) per core: 2
Core(s) per socket: 1
CPU socket(s): 1
Vendor ID: GenuineIntel
CPU family: 15
Model: 2
Stepping: 9
CPU MHz: 3391.773
# The following is the parsable format, which can be fed to other
# programs. Each different item in every column has an unique ID
# starting from zero.
# CPU,Core,Socket,Node
0,0,0,
1,0,0,

26
tests/expected/ts-lscpu-i386-intels5000phb Normal file
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@ -0,0 +1,26 @@
CPU(s): 8
Thread(s) per core: 1
Core(s) per socket: 4
CPU socket(s): 2
Vendor ID: GenuineIntel
CPU family: 6
Model: 15
Stepping: 7
CPU MHz: 1596.044
Virtualization: VT-x
L1d cache: 32K
L1i cache: 32K
L2 cache: 4096K
# The following is the parsable format, which can be fed to other
# programs. Each different item in every column has an unique ID
# starting from zero.
# CPU,Core,Socket,Node,,L1d,L1i,L2
0,0,0,,,0,0,0
1,1,0,,,1,1,0
2,2,0,,,2,2,1
3,3,0,,,3,3,1
4,4,1,,,4,4,2
5,5,1,,,5,5,2
6,6,1,,,6,6,3
7,7,1,,,7,7,3

26
tests/expected/ts-lscpu-ia64-hpmatterhorn Normal file
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@ -0,0 +1,26 @@
CPU(s): 8
Thread(s) per core: 1
Core(s) per socket: 1
CPU socket(s): 8
NUMA node(s): 3
Vendor ID: GenuineIntel
CPU family: Itanium 2
Model: 1
CPU MHz: 1300.000000
L1d cache: 16K
L1i cache: 16K
L2 cache: 256K
L3 cache: 3072K
# The following is the parsable format, which can be fed to other
# programs. Each different item in every column has an unique ID
# starting from zero.
# CPU,Core,Socket,Node,,L1d,L1i,L2,L3
0,0,0,0,,0,0,0,0
1,1,1,0,,1,1,1,1
2,2,2,0,,2,2,2,2
3,3,3,0,,3,3,3,3
4,4,4,1,,4,4,4,4
5,5,5,1,,5,5,5,5
6,6,6,1,,6,6,6,6
7,7,7,1,,7,7,7,7

20
tests/expected/ts-lscpu-ia64-hprx1620 Normal file
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@ -0,0 +1,20 @@
CPU(s): 2
Thread(s) per core: 1
Core(s) per socket: 1
CPU socket(s): 2
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: Itanium 2
Model: 2
CPU MHz: 1599.000967
L1d cache: 16K
L1i cache: 16K
L2 cache: 256K
L3 cache: 3072K
# The following is the parsable format, which can be fed to other
# programs. Each different item in every column has an unique ID
# starting from zero.
# CPU,Core,Socket,Node,,L1d,L1i,L2,L3
0,0,0,0,,0,0,0,0
1,1,1,0,,1,1,1,1

35
tests/expected/ts-lscpu-ia64-pg0 Normal file
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@ -0,0 +1,35 @@
CPU(s): 16
Thread(s) per core: 1
Core(s) per socket: 2
CPU socket(s): 8
NUMA node(s): 2
Vendor ID: GenuineIntel
CPU family: Itanium 2
Model: 0
CPU MHz: 1418.000227
L1d cache: 16K
L1i cache: 16K
L2d cache: 256K
L2i cache: 1024K
L3 cache: 6144K
# The following is the parsable format, which can be fed to other
# programs. Each different item in every column has an unique ID
# starting from zero.
# CPU,Core,Socket,Node,,L1d,L1i,L2d,L2i,L3
0,0,0,0,,0,0,0,0,0
1,1,0,0,,1,1,1,0,0
2,2,1,0,,2,2,2,1,1
3,3,1,0,,3,3,3,1,1
4,4,2,0,,4,4,4,2,2
5,5,2,0,,5,5,5,2,2
6,6,3,0,,6,6,6,3,3
7,7,3,0,,7,7,7,3,3
8,8,4,1,,8,8,8,4,4
9,9,4,1,,9,9,9,4,4
10,10,5,1,,10,10,10,5,5
11,11,5,1,,11,11,11,5,5
12,12,6,1,,12,12,12,6,6
13,13,6,1,,13,13,13,6,6
14,14,7,1,,14,14,14,7,7
15,15,7,1,,15,15,15,7,7

36
tests/expected/ts-lscpu-x86_64-hpdl585 Normal file
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@ -0,0 +1,36 @@
CPU(s): 16
Thread(s) per core: 1
Core(s) per socket: 4
CPU socket(s): 4
NUMA node(s): 4
Vendor ID: AuthenticAMD
CPU family: 16
Model: 2
Stepping: 3
CPU MHz: 2210.188
Virtualization: AMD-V
L1d cache: 512K
L1i cache: 512K
L2 cache: 512K
L3 cache: 2048K
# The following is the parsable format, which can be fed to other
# programs. Each different item in every column has an unique ID
# starting from zero.
# CPU,Core,Socket,Node,,L1d,L1i,L2,L3
0,0,0,0,,0,0,0,0
1,1,0,0,,1,1,1,1
2,2,0,0,,2,2,2,2
3,3,0,0,,3,3,3,3
4,4,1,1,,4,4,4,4
5,5,1,1,,5,5,5,5
6,6,1,1,,6,6,6,6
7,7,1,1,,7,7,7,7
8,8,2,2,,8,8,8,8
9,9,2,2,,9,9,9,9
10,10,2,2,,10,10,10,10
11,11,2,2,,11,11,11,11
12,12,3,3,,12,12,12,12
13,13,3,3,,13,13,13,13
14,14,3,3,,14,14,14,14
15,15,3,3,,15,15,15,15

20
tests/expected/ts-lscpu-x86_64-ibme326m Normal file
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@ -0,0 +1,20 @@
CPU(s): 2
Thread(s) per core: 1
Core(s) per socket: 2
CPU socket(s): 1
NUMA node(s): 1
Vendor ID: AuthenticAMD
CPU family: 15
Model: 33
Stepping: 2
CPU MHz: 1995.058
L1d cache: 1024K
L1i cache: 1024K
L2 cache: 1024K
# The following is the parsable format, which can be fed to other
# programs. Each different item in every column has an unique ID
# starting from zero.
# CPU,Core,Socket,Node,,L1d,L1i,L2
0,0,0,0,,0,0,0
1,1,0,0,,1,1,1

19
tests/expected/ts-lscpu-x86_64-necem14 Normal file
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@ -0,0 +1,19 @@
CPU(s): 2
Thread(s) per core: 2
Core(s) per socket: 1
CPU socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 15
Model: 4
Stepping: 3
CPU MHz: 3790.599
L1d cache: 16K
L2 cache: 2048K
# The following is the parsable format, which can be fed to other
# programs. Each different item in every column has an unique ID
# starting from zero.
# CPU,Core,Socket,Node,,L1d,L2
0,0,0,0,,0,0
1,0,0,0,,0,0

184
tests/input/ts-lscpu-i386-amdshanghai/proc/cpuinfo Normal file
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@ -0,0 +1,184 @@
processor : 0
vendor_id : AuthenticAMD
cpu family : 16
model : 4
model name : AMD Engineering Sample
stepping : 0
cpu MHz : 1995.158
cache size : 512 KB
physical id : 0
siblings : 4
core id : 0
cpu cores : 4
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc pni cx16 popcnt lahf_lm cmp_legacy svm extapic cr8legacy abm sse4a misalignsse 3dnowprefetch osvw ibs ts ttp tm stc 100mhzsteps hwpstate [8]
bogomips : 3992.50
processor : 1
vendor_id : AuthenticAMD
cpu family : 16
model : 4
model name : AMD Engineering Sample
stepping : 0
cpu MHz : 1995.158
cache size : 512 KB
physical id : 0
siblings : 4
core id : 1
cpu cores : 4
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc pni cx16 popcnt lahf_lm cmp_legacy svm extapic cr8legacy abm sse4a misalignsse 3dnowprefetch osvw ibs ts ttp tm stc 100mhzsteps hwpstate [8]
bogomips : 3991.05
processor : 2
vendor_id : AuthenticAMD
cpu family : 16
model : 4
model name : AMD Engineering Sample
stepping : 0
cpu MHz : 1995.158
cache size : 512 KB
physical id : 0
siblings : 4
core id : 2
cpu cores : 4
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc pni cx16 popcnt lahf_lm cmp_legacy svm extapic cr8legacy abm sse4a misalignsse 3dnowprefetch osvw ibs ts ttp tm stc 100mhzsteps hwpstate [8]
bogomips : 3993.85
processor : 3
vendor_id : AuthenticAMD
cpu family : 16
model : 4
model name : AMD Engineering Sample
stepping : 0
cpu MHz : 1995.158
cache size : 512 KB
physical id : 0
siblings : 4
core id : 3
cpu cores : 4
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc pni cx16 popcnt lahf_lm cmp_legacy svm extapic cr8legacy abm sse4a misalignsse 3dnowprefetch osvw ibs ts ttp tm stc 100mhzsteps hwpstate [8]
bogomips : 3993.27
processor : 4
vendor_id : AuthenticAMD
cpu family : 16
model : 4
model name : AMD Engineering Sample
stepping : 0
cpu MHz : 1995.158
cache size : 512 KB
physical id : 1
siblings : 4
core id : 0
cpu cores : 4
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc pni cx16 popcnt lahf_lm cmp_legacy svm extapic cr8legacy abm sse4a misalignsse 3dnowprefetch osvw ibs ts ttp tm stc 100mhzsteps hwpstate [8]
bogomips : 3990.03
processor : 5
vendor_id : AuthenticAMD
cpu family : 16
model : 4
model name : AMD Engineering Sample
stepping : 0
cpu MHz : 1995.158
cache size : 512 KB
physical id : 1
siblings : 4
core id : 1
cpu cores : 4
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc pni cx16 popcnt lahf_lm cmp_legacy svm extapic cr8legacy abm sse4a misalignsse 3dnowprefetch osvw ibs ts ttp tm stc 100mhzsteps hwpstate [8]
bogomips : 3990.09
processor : 6
vendor_id : AuthenticAMD
cpu family : 16
model : 4
model name : AMD Engineering Sample
stepping : 0
cpu MHz : 1995.158
cache size : 512 KB
physical id : 1
siblings : 4
core id : 2
cpu cores : 4
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc pni cx16 popcnt lahf_lm cmp_legacy svm extapic cr8legacy abm sse4a misalignsse 3dnowprefetch osvw ibs ts ttp tm stc 100mhzsteps hwpstate [8]
bogomips : 3990.04
processor : 7
vendor_id : AuthenticAMD
cpu family : 16
model : 4
model name : AMD Engineering Sample
stepping : 0
cpu MHz : 1995.158
cache size : 512 KB
physical id : 1
siblings : 4
core id : 3
cpu cores : 4
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 5
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc pni cx16 popcnt lahf_lm cmp_legacy svm extapic cr8legacy abm sse4a misalignsse 3dnowprefetch osvw ibs ts ttp tm stc 100mhzsteps hwpstate [8]
bogomips : 3989.99

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index0/level vendored Normal file
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@ -0,0 +1 @@
1

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index0/shared_cpu_map vendored Normal file
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@ -0,0 +1 @@
00000001

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index0/size vendored Normal file
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@ -0,0 +1 @@
512K

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index0/type vendored Normal file
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@ -0,0 +1 @@
Data

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index1/level vendored Normal file
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@ -0,0 +1 @@
1

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index1/shared_cpu_map vendored Normal file
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@ -0,0 +1 @@
00000001

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index1/size vendored Normal file
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@ -0,0 +1 @@
512K

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index1/type vendored Normal file
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@ -0,0 +1 @@
Instruction

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index2/level vendored Normal file
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@ -0,0 +1 @@
2

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_map vendored Normal file
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@ -0,0 +1 @@
00000001

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index2/size vendored Normal file
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@ -0,0 +1 @@
512K

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index2/type vendored Normal file
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@ -0,0 +1 @@
Unified

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index3/level vendored Normal file
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@ -0,0 +1 @@
3

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index3/shared_cpu_map vendored Normal file
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@ -0,0 +1 @@
00000001

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index3/size vendored Normal file
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@ -0,0 +1 @@
6144K

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/cache/index3/type vendored Normal file
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@ -0,0 +1 @@
Unified

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/topology/core_siblings Normal file
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@ -0,0 +1 @@
0000000f

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu0/topology/thread_siblings Normal file
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@ -0,0 +1 @@
00000001

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index0/level vendored Normal file
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@ -0,0 +1 @@
1

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index0/shared_cpu_map vendored Normal file
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@ -0,0 +1 @@
00000002

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index0/size vendored Normal file
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@ -0,0 +1 @@
512K

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index0/type vendored Normal file
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@ -0,0 +1 @@
Data

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index1/level vendored Normal file
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@ -0,0 +1 @@
1

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index1/shared_cpu_map vendored Normal file
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@ -0,0 +1 @@
00000002

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index1/size vendored Normal file
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@ -0,0 +1 @@
512K

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index1/type vendored Normal file
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@ -0,0 +1 @@
Instruction

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index2/level vendored Normal file
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@ -0,0 +1 @@
2

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_map vendored Normal file
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@ -0,0 +1 @@
00000002

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index2/size vendored Normal file
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@ -0,0 +1 @@
512K

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index2/type vendored Normal file
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@ -0,0 +1 @@
Unified

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index3/level vendored Normal file
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@ -0,0 +1 @@
3

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index3/shared_cpu_map vendored Normal file
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@ -0,0 +1 @@
00000002

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index3/size vendored Normal file
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@ -0,0 +1 @@
6144K

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/cache/index3/type vendored Normal file
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@ -0,0 +1 @@
Unified

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/topology/core_siblings Normal file
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@ -0,0 +1 @@
0000000f

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu1/topology/thread_siblings Normal file
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@ -0,0 +1 @@
00000002

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@ -0,0 +1 @@
1

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tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu2/cache/index0/shared_cpu_map vendored Normal file
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@ -0,0 +1 @@
00000004

1
tests/input/ts-lscpu-i386-amdshanghai/sys/devices/system/cpu/cpu2/cache/index0/size vendored Normal file
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@ -0,0 +1 @@
512K

1
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